The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generations. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be fabricated) has decreased.
A chemical mechanical polishing (CMP) process is used in the fabrication of ICs. As an IC is built up layer by layer from a surface of a semiconductor wafer, the CMP process is used to planarize the uppermost layer or layers to provide a leveled surface for fabrication.
There are challenges in fabricating of advanced integrated circuit (IC) involving CMP process.